1. Field of the Invention
The present invention relates to a data transfer circuit and, more particularly, a data transfer circuit for transferring data synchronously with a clock signal.
2. Description of the Background Art
Conventionally, as a method of transferring data between semiconductor integrated circuit devices or in a semiconductor integrated circuit device, a method of precharging two data transfer lines disposed between a transmission side circuit and a reception side circuit once to the same potential (for example, xe2x80x9cHxe2x80x9d level) and setting one of the two data transfer lines selected according to transfer data to the xe2x80x9cLxe2x80x9d level, thereby transferring data xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d is known.
According to the data transfer method, each time data is transferred, the two data transfer lines have to be precharged once to the xe2x80x9cHxe2x80x9d level.
Consequently, when the data transfer lines become longer and wiring capacity and wiring resistance accordingly increase, time necessary for precharging becomes long, and it causes a problem such that the data transfer rate deteriorates.
Japanese Patent Laying-Open No. 2000-132970 discloses a method in which three data transfer lines are disposed between a transmission side circuit and a reception side circuit, while data is transferred by using two data transfer lines, the remaining data transfer line is precharged to the xe2x80x9cHxe2x80x9d level and, then, data is transferred by using the two data transfer lines of the xe2x80x9cHxe2x80x9d level including the precharged data transfer line among the three data transfer lines, thereby preventing deterioration in data transfer rate.
Since precharging is performed during data transfer, the data transfer system has, however, a problem that the power consumption is high as compared with the conventional technique of performing precharging after data transfer.
Japanese Patent Laying-Open No. 2000-339968 discloses a method of transferring charges between a data transfer line to be precharged and a data transfer line changed from the xe2x80x9cHxe2x80x9d level to the xe2x80x9cLxe2x80x9d level for data transfer, thereby reducing power consumption.
This method, however, has a problem of a low transfer rate due to a circuit operation of electrically connecting the data transfer lines at the time of data transfer to transfer charges, interrupting the electrical connection and, after that, further changing the potential of the data transfer line by a driver.
An object of the invention is to provide a low-power data transfer circuit having a high data transfer rate.
A data transfer circuit, includes: three data signal lines; a first selection circuit for selecting two data signal lines having first and second potentials which are complementary to each other for transmitting data, out of the three data signal lines and for precharging a non-selected data signal line to the first potential; and a second selection circuit for selectively and electrically connecting the two data signal lines selected by the first selection circuit out of the three data signal lines to a reception side circuit, and the first selection circuit includes a driver circuit provided corresponding to each of the three data signal lines and connected between the first and third potentials and the second potential is set to a level between the first and third potentials.
By using two out of three data transfer lines to transfer data and precharging the remaining one data transfer line while data is transferred, data transfer can be performed efficiently and maintaining one of potentials of the selected two data transfer lines at a first potential as a potential for precharging and setting the other potential to a second potential between a third potential (for example, ground potential GND) and the first potential, power consumption to precharge the data transfer line to the first potential can be reduced.
Preferably, the first selection circuit selects two data signal lines of same potential levels out of the three data signal lines, on the basis of the potentials of predetermined two data signal lines out of the three data signal lines.
A data transfer line to be selected next can be selected based on the potentials of two data transfer lines out of the three data transfer lines. Consequently, it is unnecessary to supply a selection signal from the outside, and the number of components can be reduced.
Preferably, the second selection circuit includes an amplifying circuit for amplifying a potential difference between the two data signal lines selected by the first selection circuit out of the three data signal lines, and
on the basis of the potential difference amplified by the amplifying circuit, selectively and electrically connects the two data signal lines selected by the first selection circuit to the reception side circuit.
The data transfer lines used for data transfer out of the three data transfer lines can be selected by a potential difference of the two data transfer lines. Thus, it is unnecessary to supply a selection signal from the outside, and the number of components can be reduced.
Preferably, the data transfer circuit further includes a latching circuit for holding the potentials of predetermined two data signal lines out of the three data signal lines as binary data; and the first selection circuit selects two data signal lines out of the three data signal lines on the basis of the binary data held by the latching circuit.
Particularly the first selection circuit includes a logic control section for selecting two data signal lines out of the three data signal lines and selecting one of the first potential and third potential supplied by the potential supply source to each of the three data signal lines.
Particularly the driver circuit is activated in response to a driver enable signal, and the second potential is set in accordance with an active period of the driver enable signal.
The semiconductor integrated circuit includes: a memory cell array having a plurality of memory cells arranged in a matrix; an input/output control circuit for outputting data held in a selected memory cell designated on the basis of an address signal out of the memory cell; a data buffer circuit for outputting a reading data read from the input/output control circuit to an external output-terminal a data transfer circuit placed between the input/output control circuit and the data buffer circuit and for transmitting the reading data to the data buffer circuit a first input/output line for transmitting the reading data from the input/output control circuit to the data transfer circuit and a second input/output line for transmitting the reading data from the data transfer circuit to the data buffer circuit, and the data transfer circuit includes; three data signal lines are longer than the first and second input/output line; a first selection circuit for selecting two data signal lines whose potentials change to first and second potentials which are complementary to each other in accordance with the data to be transmitted out of the three data signal lines and for precharging a non-selected data signal line to the first potential; a second selection circuit for selectively and electrically connecting the two data signal lines selected by the first selection circuit out of the three data signal lines to a reception side circuit; and the first selection circuit having a driver circuit provided corresponding to each of the three data signal lines and connected between the first potential and third potential and the logic control section for selecting two data signal lines out of the three data signal lines in conjunction with selecting one of the first potential and third potential supplied by the potential supply source to each of the three data signal lines and the driver circuit activates on the basis of a driver enable signal, and the second potential is set by a period of time during supplying the driver enable signal the second selection circuit having an amplifying circuit for amplifying a potential difference between the two data signal lines selected by the first selection circuit out of the three data signal lines, and on the basis of the potential difference amplified by the amplifying circuit, selectively and electrically connects the two data signal lines having selected by the first selection circuit to the second input/output line.
The semiconductor integrated circuit of the invention uses two out of three data transfer lines to transfer data and precharges the remaining one data transfer line while data is transferred, thereby enabling data transfer to be performed efficiently and by maintaining one of potentials of the selected two data transfer lines at a first potential as a potential for precharging and setting the other potential to a second potential between a third potential (for example, ground potential GND) and the first potential, power consumption to precharge the data transfer line to the first potential can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.